Over the last few decades, the electronics industry has developed semiconductor technology to fabricate small, highly integrated electronic devices. Many semiconductor devices are now formed by vertical stacking of device layers, including multiple layers of conductive lines with interconnects between layers. As these devices become smaller, there is a need for increasingly narrow conductive lines and interconnects to form circuit pathways within these devices. These conductive lines and interconnects are typically formed using metals, including, for example, aluminum, tungsten, and copper.
In a multilevel architecture, layers of metal conductive lines which define circuit pathways are separated from each other by interlevel dielectrics. In a typical process scheme, a first metal layer is deposited and patterned to form a first set of conductive lines. This is followed by deposition of a dielectric layer over the first set of conductive lines. Vias are etched through the dielectric layer to the underlying conductive lines and then filled with metal to establish interlayer conduction. In conventional processing methods, the metal which fills the vias typically extends beyond the via when deposited. This excess metal is removed by, for example, chemical-mechanical polishing or etch back. A second metal layer may then be formed over the dielectric layer and patterned into a second set conductive lines.
With current aggressive design rules, it is not always possible to have complete overlap of conductive lines with underlying vias. This typically leaves at least a portion of the vias exposed during the etch process in which second set of conductive lines are patterned. A recess in the exposed portion of the vias may be formed during this process. For example, if an aluminum conductive line is formed over the via and the aluminum conductive line does not completely overlap the underlying via, then there is a possibility that a portion of the via may be etched during the formation of the conductive lines, which typically includes one or more metal etching steps.
Tungsten is used to fill the vias in order to reduce the amount of recessing during subsequent processing steps. Tungsten-filled vias provide adequate selectivity during metal etching steps. However, the presence of tungsten in the path of current flow may lead to flux divergence in the metal lines at the tungsten/metal interfaces resulting in the degradation of the electromigration resistance.
To address this issue, aluminum and aluminum alloys have been suggested for incorporation in the vias. In addition to reducing via resistance, aluminum vias may also show better electromigration resistance. The use of aluminum in vias is expected to become more important as the device dimensions become smaller. Conventional techniques include filling the vias with tungsten or aluminum, polishing or etching back the tungsten or aluminum to remove excess deposits outside of the via, and then depositing a second metal layer for making the conductive lines.
When aluminum is incorporated in the vias, a conventional metal etch technique cannot be used to form the conductive lines, which are also typically aluminum, because the aluminum in the vias may be exposed to metal etchants which may create recessing in the vias. This recessing can lead to electromigration failure. Furthermore, recesses in the vias may trap chemicals or gases during subsequent processing steps. These chemicals and gases may lead to device degradation over time. In addition, the effective thinning of the via due to the presence of the recess increases the current density through that portion of the via which may lead to local overheating and electromigration. Thus, there is a need for an improved method for forming vias and conductive lines in a semiconductor device to prevent the formation of recesses in non-overlapping portions of the via during processing.